1. Field of the Invention
The present invention relates to a method for calculating the bidimensional discrete cosine transform and the circuitry for implementing such a method.
2. Description of the Related Art
As is well-known, the encoding of television signals is made efficient by the use of the discrete cosine transform (DCT) having dimension 8*8, or, more generally M*M, where M is a power of 2.
In commercial television, the number of samples to be processed is very high (typically over 10 millions of samples per second, and for digital studio format on the order of 27 millions of samples per second), and, in particular, for high-definition television (HDTV), the sample flow on which it is necessary to operate the DCT is higher than 100 millions per second; in HDTV, many processors operating in parallel are used, but obviously a circuit that performs the bidimensional DCT faster is desirable because it reduces the number of processors which must be used.
There some well-known integrated circuits for performing the bidimensional DCT. However, to increase the calculation speed and at the same time keep the number of logic gates within reasonable limits, these circuits must perform the calculations in serial arithmetic.
See, in particular, the articles by F. Jutland, N. Demassieux, G. Concordel, J. Guichard, E. Cassimatis, "A single chip video rate 16*16 Discrete Cosine Transform" (Proc. Int. Conf. Acoustic, Speech and Signal Processing 1986) and S. Cucchi, F. Molo, "DCT based television coded for DS3 digital transmission" (130th SMPTE Technical Conference 1988), which describe circuits for executing the bidimensional DCT using serial arithmetic. In particular, the article by Cucchi and Molo describes the bidimensional DCT 8*8, made of two monodimensional DCTs of dimension 8, followed by the calculation scheme proposed by Chen, Fralick and Smith in the article "A fast computational algorithm for the Discrete Cosine Transform" (IEEE Trans. on Comm., September 1977).
The bidimensional DCT of dimension M*M is executed by decomposing it into two transforms of dimension M, and serial arithmetic is used for the calculation thereof. For precision and accuracy, numbers are represented with B binary ciphers, where B is usually equal to 16; it must be noted that the words coming into the DCT and the words out from the same DCT (the calculation results) are under 16 bits (usually from 8 to 12 bits). As the words on the DCT is applied enter the calculation circuit under the form of parallel bits at a speed R.sub.p, the words are transformed from parallel into serial form before the two DCTs are performed (and an inverse transform is performed before sending to the words are outputted from the transform). The bit speed R.sub.s in the inside of the processor DCT is given by: ##EQU1## where M is the dimension of the DCT, and 16 is the number of serial bits of each word used for making the calculations. In the case of a DCT having dimension 8 (M=8), (normally the best compromise between the complexity and efficiency), it is: EQU R.sub.s =2R.sub.p
i.e. he transfer speed of bits in words of serial form is twice the speed of the words coming into and out of the DCT processor, which on the one hand requires that the DCT processor being supplied with a clock frequency twice the frequency of the incoming and outgoing words, and on the other hand requires higher frequency calculating elements or equivalently requires keeping speed at which the bits are processed in the inside of the processor constant to limit the speed of incoming and outgoing words.